Physical Implementation Engineer Graduate
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France
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INFORMATICS / COMPUTER SCIENCES , Electronic Engineering
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Deadline Deadline: Continuous
Meeting Area, Frequency and Power requirements is one of most challenging activities in CPU development. You will work in close loop with micro-architecture designers and standards cells/Macro designers to improve key metrics as well as overall quality of designs targeting 7nm and below technology nodes. Using a broad array of skills, you will also be part of a complete implementation flow development from synthesis to GDS2, including static timing analysis, IR drop analysis and equivalence checking.
Key Accountabilities/Responsibilities
As a member of the Sophia Antipolis CPU implementation team:
Working in close loop with CPU design team, you will identify critical paths and timing bottlenecks across IP development, enabling correct trade-off between the various performance metrics of the designs (frequency, IPC, power, area)
You will have to produce Power/Performance/area figures and help improving CPU micro architecture.
You will take part of existing CPU benchmarking to get the best possible Quality of Results.
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